This invention relates to an integrated monolithic structure containing one or more electronic systems and, in particular, to a substrate containing one or more integrated circuit chips placed in the substrate such that the top surface of each chip contains electrically conductive lands or electrically conductive pads and is substantially coplanar with the top surface of the substrate such that conductive traces can be formed over the top surfaces of the integrated circuit chips and the substrate to interconnect integrated circuit chips into one or more desired electronic systems.
For many years, the semiconductor industry has been attempting to fabricate a system on a chip. In particular, the industry has attempted to combine linear and digital circuitry on the same chip and often to include memory on the chip to provide an electronic system on a single integrated circuit chip. Unfortunately, the additional processing steps create yield loss such that if a single component of the chip fails, all components on the chip are useless. As a result, multi-chip modules in particular are commonly used to create electronic systems.
Some companies have combined logic and memory on a chip. Microprocessors, programmable logic and graphics circuits, in particular, incorporate logic circuitry together with memory.
Accordingly, there exists a need for a monolithic, integrated structure which can incorporate the functions represented by semiconductor chips fabricated using different technologies, such as analog and digital, so as to form one or more partial or entire electronic systems.
In accordance with this invention, one or more integrated circuit chips is placed or are combined in a substrate such that the chip or chips can be electrically contacted or interconnected using standard photolithographic processes to form a single integrated circuit package or an electronic system. The chips can be from different technologies, even from substrates that are totally incompatible. Thus, chips fabricated using silicon and gallium-arsenide technology can be placed in the monolithic structure of this invention and interconnected so as to operate together as part of an electronic system.
In addition, integrated circuit chips fabricated using normal 100 silicon can be combined using the methods of this invention with integrated circuit chips fabricated using 111 silicon as well as with gallium-arsenide chips, for example, to yield a composite structure.
The process of this invention allows semiconductor chips using different technologies to be combined in a single monolithic, integrated structure of high reliability and to be interconnected using standard photolithographic processing currently available in the semiconductor industry and/or the printed circuit board industry.
In accordance with a process of this invention, two or more integrated circuit chips of the same type or disparate types are placed in two or more cavities, respectively, in a substrate. Adhesive bonding material is placed on the surface of the cavity and in the interconnect spaces between the integrated circuit chips and the cavity walls and allowed to set thereby to adherently hold the integrated circuit chips in their respective cavities. The chips are placed in the cavities such that conductive pads face outward from the cavity and are visible as well as being substantially in the same plane as the top surface of the substrate. A conductive layer is then deposited over the top surface of the substrate and the exposed surfaces and conductive pads of the integrated circuit chips contained in the substrate cavities. Standard photolithographic techniques are then used to mask and etch the conductive layer to form a conductive interconnect pattern to interconnect the two or more chips into the desired electronic system.
In accordance with one embodiment of this invention, the integrated circuit chips can be of different types, different materials and carry out different functions, and yet when interconnected together, form a unitary monolithic electronic system of high quality and great reliability.
In accordance with another embodiment of this invention, a plastic substrate is made with cavities having sides with fixed angles such that cross-sections of the cavities are trapezoidal. The substrate may be manufactured using a mold that is custom created for each type package system. Typically, each package contains a single device or a multichip module and is substantially smaller than a standard 18 inch by 24 inch plastic substrate. Therefore, the routing pattern for each package is stepped and repeated across the plastic substrate to create a plurality of identical packages.
A plastic such as Mylar, Melinex or Delrin may be injected into the mold to produce the substrate with the desired cavities with the specific angled sidewalls, which may vary from vertical to plus or minus 45 degrees or greater. Other thermoplastic, thermoset or composite plastics could be used. All cavities are through-hole cavities and have their largest dimensions on the same side of the substrate. The thickness of the substrate can vary from a few thousandths of an inch to more than one quarter of an inch. Typically, the cavities are similar in thickness to the integrated circuits that are to be inserted into them. However, if the cavities are made using angled sidewalls, components with similar angled sides will naturally center themselves when inserted.
A planarizing layer, such as a planar stainless steel or quartz plate, of the same dimensions as the substrate, is temporarily attached to the side of the substrate where the cavity dimensions are smaller. The planarizing layer may be coated with a soft, non-sticking film, such as but not limited to Teflon. Various methods can be used to attach the substrate to the planarizing layer including clamps or temporary adhesives.
Integrated circuits and other active or passive devices that have their bonding pads on the topside in either an array or peripheral pattern are manufactured with angled sidewalls that typically match the angles of the cavities into which they will be inserted. The topsides of the integrated circuits are made to match the smaller dimensions of the substrate cavities. The angles on the sidewalls of the integrated circuits in one embodiment are made using a diamond saw whose blade has a specific angle which may match the angle created in the cavity. Alternatively, anisotropic etching can also be used to create specific angles of the sidewalls on the integrated circuits that match angles of the sidewalls of the cavities in the substrate.
The integrated circuits are inserted into their matching cavities on the substrate with their topsides on the matching bottom of the cavity and their backsides exposed. A prepreg layer (resin implanted with glass or aramid fiber) is applied to the backside of the integrated structure (i.e. to the exposed backsides of the integrated circuits and the adjacent exposed surface of the substrate) and the temperature and pressure are increased causing the prepreg material to soften and flow around the integrated circuits and into all crevices that may exist between the integrated circuits and the substrate. The temperature is lowered, the pressure is released and the cured prepreg permanently holds each integrated circuit in its respective cavity, the top side of each integrated circuit being forced into coplanarity with the top surface of the substrate. The planarizing layer may then be removed to expose the top sides with conductive pads of the integrated circuits and the coplanar top surface of the substrate.
Metal, such as copper, is deposited over the entire top surface of the structure, covering the original substrate as well as the topsides and the bonding pads of the integrated circuits. The metal may be plated or applied by other processes such as sputtering or evaporation. A photosensitive material is then applied to the metal layer and the interconnect pattern is defined and etched in a well known manner to form the desired electrically conductive interconnect pattern. In some cases it may be desirable to connect the integrated circuits using multi-layer metal patterns with or without ground or Vcc planes inserted between the routing layers.
One of the advantages of this invention is that bonding pads on the integrated circuit chips can be positioned above the circuitry formed in the integrated circuit chip rather than maintained solely on the periphery of the integrated circuit chip. Prior art bonding pads were located on the periphery of the chip to prevent the pressure generated during thermal compression bonding of lead wires to the bonding pads from damaging underlying circuitry. This invention allows such bonding pads or conductive lands to be placed on dielectric over the circuitry because the electrical connections between the bonding pads and external circuitry are implemented by electrically conductive leads deposited on the top surfaces of the integrated circuit chips and the top surface of the substrate using a process which creates no pressure on the underlying circuitry. As a result, smaller integrated circuit chips can be fabricated thereby allowing manufacturers to place more die on a wafer and thus substantially reduce the cost of the resulting die. Consequently, the cost of the resulting packaged integrated circuit chip is also reduced. Furthermore, this invention allows standard semiconductor or printed circuit board processing techniques to be used to fabricate a plurality of integrated circuit packages at the same time thereby further reducing the cost of each package. When printed circuit board fabrication technologies are used in accordance with this invention, very large numbers of semiconductor die can be electrically interconnected to leads on a substrate using the techniques of this invention. The subsequent structure can then be further processed in accordance with well known techniques to complete semiconductor packages for the die contained on the substrate. The final structure can then be singulated to separate each of the packaged die.
An additional advantage of this invention is that solder bumps used for assembling flip chip packages can be eliminated. Environmentally, since solder bumps contain lead, this is a tremendous advantage over the prior art.
The structure of this invention provides the same array patterns that can be used in the prior art flip chip arrangement but avoids the blind contacts required using the flip chip technology, eliminates the lead bumps, eliminates underfill (used to prevent cracking of the die), and distributes the contact interface between chip and substrate, eliminating thermally induced cracking of the die. The result is to increase the reliability and quality of the semiconductor systems fabricated in accordance with this invention.
In one embodiment, the conductive layer formed on the top surfaces of the integrated circuit chips and the substrate is copper. Once fabricated, the electrically conductive interconnect lead pattern is capable of being visually inspected. Thus, the quality of the resulting structure is significantly improved over the prior art, as is the yield.
Should a single cavity only be formed in the substrate, then the structure of this invention provides a compact, easily and/or economically manufactured, package for the integrated circuit chip which eliminates substantial cost from the final integrated circuit chip package. This invention results in an integrated circuit chip package having electrical connections to the integrated circuit chip which have lower inductance and capacitance than prior art packages and which provides a lower cost, thinner and higher performing package than in the prior art. The integrated circuit chip package of this invention can be fabricated using a large substrate in which a plurality (such as thousands) of identical cavities are formed to receive a corresponding plurality (i.e. thousands) of identical integrated circuit chips. Upon completion of the process, the resulting composite structure can then be singulated using standard scoring processes in the semiconductor and printed circuit arts. If desired a plurality of non-identical integrated circuits can be placed in a plurality of non-identical cavities (which dimensionally match the dimensions of the non-identical integrated circuits), in the same substrate which can then be singulated as described above.
This invention will be more clearly understood in conjunction with the following detailed description taken together with the following drawings.